CPE 405: VLSI Design & System-on-Chip (SoC) Architecture

By PAMCET Learning Team

progress: 0 of 24 lessons0% complete

now_playing

CPE 405: VLSI Design & System-on-Chip (SoC) Architecture

Rating

Enrolled Students0

Last UpdateSep 17, 2026

About Course

CMOS layout, stick diagrams, Elmore delay, AMBA bus (AXI/AHB/APB), IP cores, Design for Testability (DFT), and ASIC flow.

Course Includes

8 Chapters
16 Lectures
24h Course Duration
Skill Level advanced
Taught in English
Lifetime Access

Course Includes

8 Chapters
16 Lectures
24h Course Duration
Skill Level advanced
Taught in English
Lifetime Access

What You'll Learn

Draw CMOS layout stick diagrams and apply scalable lambda design rules for DRC and LVS clean circuits.
Calculate propagation delays, parasitic capacitances, and Elmore RC delays in CMOS combinational networks.
Design interconnect architectures using the ARM AMBA on-chip bus family (AXI, AHB, APB).
Integrate reusable third-party intellectual property (IP) cores into cohesive System-on-Chip (SoC) platforms.
Implement Design for Testability (DFT) circuits including scan chains, scan flip-flops, and Built-In Self-Test (BIST).

Requirements

Completion of CPE 301 and CPE 304.

Instructor

PAMCET Learning Team

The PAMCET Learning Team is the institutional curriculum and content group behind course publishing on this platform. PAMCET (Professional and Academic Management Centre for Education and Training) is operated by Digitpen Hub Ltd, a company registered in Lagos, Nigeria. Courses credited to the PAMCET Learning Team are structured, organized, and published centrally by the platform rather than authored by a single named individual instructor — each course's syllabus, learning outcomes, and content are reviewed before publication under this institutional account. For questions about a specific course or to report a content issue, please use the platform's Help & Support or Contact Us pages.

Loading tabs...

Course Curriculum

1. CMOS Integrated Circuit Fundamentals: Inverter Transfer Characteristics, Noise Margins, and Parasitics: Theoretical Foundations, Mathematical Modeling & System Architecture

1 hour 30 minutes

2. CMOS Integrated Circuit Fundamentals: Inverter Transfer Characteristics, Noise Margins, and Parasitics: Worked Engineering Problems, Design Computations & Simulation Protocols

1 hour 30 minutes

3. Chapter 1 Formative Assessment: CMOS Integrated Circuit Fundamentals: Inverter Transfer Char

CPE 405: VLSI Design & System-on-Chip (SoC) Architecture

Rating

Enrolled Students0

Last UpdateSep 17, 2026

About Course

CMOS layout, stick diagrams, Elmore delay, AMBA bus (AXI/AHB/APB), IP cores, Design for Testability (DFT), and ASIC flow.

Course Includes

8 Chapters
16 Lectures
24h Course Duration
Skill Level advanced
Taught in English
Lifetime Access

Course Includes

8 Chapters
16 Lectures
24h Course Duration
Skill Level advanced
Taught in English
Lifetime Access

What You'll Learn

Draw CMOS layout stick diagrams and apply scalable lambda design rules for DRC and LVS clean circuits.
Calculate propagation delays, parasitic capacitances, and Elmore RC delays in CMOS combinational networks.
Design interconnect architectures using the ARM AMBA on-chip bus family (AXI, AHB, APB).
Integrate reusable third-party intellectual property (IP) cores into cohesive System-on-Chip (SoC) platforms.
Implement Design for Testability (DFT) circuits including scan chains, scan flip-flops, and Built-In Self-Test (BIST).

Requirements

Completion of CPE 301 and CPE 304.