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B.Eng DegreeFaculty of Faculty of Engineering & TechnologyComputer Engineering
CPE 401: Advanced Computer Architecture & Parallel Computing
ILP, superscalar, out-of-order execution (Tomasulo), TLP, multi-core cache coherence (MESI), vector SIMD, and GPUs.
Course Overview
ILP, superscalar, out-of-order execution (Tomasulo), TLP, multi-core cache coherence (MESI), vector SIMD, and GPUs. Curriculum Structure & Core Modules: • 1. Instruction-Level Parallelism (ILP): Superscalar Processors, Dynamic Execution, and Branch Prediction • 2. Dynamic...
What You'll Learn
- Analyze instruction-level parallelism (ILP) limits and dynamic scheduling using Tomasulo's algorithm.
- Evaluate multi-core Symmetric Multiprocessing (SMP) architectures and interconnection network topologies.
- Trace snooping and directory-based cache coherence protocols (MSI, MESI, MOESI) under concurrent writes.
- Compare relaxed memory consistency models (Sequential Consistency, Total Store Order, Weak Ordering).
- Design SIMD vector processing routines and analyze GPU stream multiprocessor architectures.
Requirements
- Completion of CPE 301.
Degree Programme Curriculum Context
This course is a curriculum unit of the Bachelor of Engineering (B.Eng.) in Computer Engineering degree framework in Nigeria.
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Course Curriculum
Open-access academic curriculum. All foundational lectures available to read free.
8 Chapters
•16 Lecture
•24h
1. Instruction-Level Parallelism (ILP): Superscalar Processors, Dynamic Execution, and Branch Prediction: Theoretical Foundations, Mathematical Modeling & System Architecture
CPE 401 • 400 Level • Computer Engineering Chapter 1: Instruction-Level Parallelism (ILP): Superscalar Processors, Dynamic Execution, and Branch Prediction — Theoretical Foundations, Mathematical Modeling & System Architecture Course: CPE 401: Advanced Computer Architecture & Parallel Computing Curriculum: NUC-CCMAS-CPE Accreditation: COREN-CPE-OBE Standard: IEEE/ACM-CE2024 1....
2. Instruction-Level Parallelism (ILP): Superscalar Processors, Dynamic Execution, and Branch Prediction: Worked Engineering Problems, Design Computations & Simulation Protocols
CPE 401 • 400 Level • Computer Engineering Chapter 1: Instruction-Level Parallelism (ILP): Superscalar Processors, Dynamic Execution, and Branch Prediction — Worked Engineering Problems, Design Computations & Simulation Protocols Course: CPE 401: Advanced Computer Architecture & Parallel Computing Curriculum: NUC-CCMAS-CPE Accreditation: COREN-CPE-OBE Practice: COREN ERM / IEEE...
1 hour 30 minutes
3. Chapter 1 Formative Assessment: Instruction-Level Parallelism (ILP): Superscalar Processors,
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Instructor
PAMCET Learning Team
Institutional Course Curation · PAMCET
Qualifications:
PAMCET Learning Team — Institutional Course Curation, Digitpen Hub LtdMy Skills:
- Curriculum Curation
- Course Content Review
- Learning Outcome Design
- Course Publishing & Quality Assurance
- Platform Content Operations
Reviews
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Free
Course Includes
8 Chapters
16 Lectures
2 - 4 weeks
Skill Level advanced
Taught in English
Lifetime Access
Certification of Completion
Category: University - Computer Engineering
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