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B.Eng DegreeFaculty of Faculty of Engineering & TechnologyComputer Engineering
CPE 304: FPGA Design & Hardware Description Languages (VHDL/Verilog)
FPGA internal architecture (LUTs/BRAM/DSP), Verilog HDL modeling, behavioral synthesis, testbenches, and timing constraints.
Course Overview
FPGA internal architecture (LUTs/BRAM/DSP), Verilog HDL modeling, behavioral synthesis, testbenches, and timing constraints. Curriculum Structure & Core Modules: • 1. Programmable Logic Evolution: ROMs, PALs, PLAs, CPLDs, and Modern SRAM-Based FPGAs • 2. FPGA Internal...
What You'll Learn
- Differentiate CPLD and FPGA architectures: Configurable Logic Blocks (CLBs), LUTs, carry chains, and DSP slices.
- Write robust, synthesizable Verilog HDL code for complex combinational and sequential digital systems.
- Design synchronous finite state machines (FSM) in Verilog with safe state encodings and glitch-free outputs.
- Construct comprehensive Verilog testbenches with self-checking assertions and clock generation routines.
- Synthesize, map, place-and-route digital designs using EDA tools (Vivado/Quartus) and meet timing constraints.
Requirements
- Completion of CPE 208 and CPE 301.
Degree Programme Curriculum Context
This course is a curriculum unit of the Bachelor of Engineering (B.Eng.) in Computer Engineering degree framework in Nigeria.
Earn Your Certificate
Showcase your skills with a certificate! Complete the course, submit your project, and earn your certificate. Here's a sample of what you'll receive to show off your accomplishments.
Course Curriculum
Open-access academic curriculum. All foundational lectures available to read free.
8 Chapters
•16 Lecture
•24h
1. Programmable Logic Evolution: ROMs, PALs, PLAs, CPLDs, and Modern SRAM-Based FPGAs: Theoretical Foundations, Mathematical Modeling & System Architecture
CPE 304 • 300 Level • Computer Engineering Chapter 1: Programmable Logic Evolution: ROMs, PALs, PLAs, CPLDs, and Modern SRAM-Based FPGAs — Theoretical Foundations, Mathematical Modeling & System Architecture Course: CPE 304: FPGA Design & Hardware Description Languages (VHDL/Verilog) Curriculum: NUC-CCMAS-CPE Accreditation: COREN-CPE-OBE Standard: IEEE/ACM-CE2024 1. Pedagogical...
2. Programmable Logic Evolution: ROMs, PALs, PLAs, CPLDs, and Modern SRAM-Based FPGAs: Worked Engineering Problems, Design Computations & Simulation Protocols
CPE 304 • 300 Level • Computer Engineering Chapter 1: Programmable Logic Evolution: ROMs, PALs, PLAs, CPLDs, and Modern SRAM-Based FPGAs — Worked Engineering Problems, Design Computations & Simulation Protocols Course: CPE 304: FPGA Design & Hardware Description Languages (VHDL/Verilog) Curriculum: NUC-CCMAS-CPE Accreditation: COREN-CPE-OBE Practice: COREN ERM / IEEE Design Sta...
1 hour 30 minutes
3. Chapter 1 Formative Assessment: Programmable Logic Evolution: ROMs, PALs, PLAs, CPLDs, and M
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Instructor
PAMCET Learning Team
Institutional Course Curation · PAMCET
Qualifications:
PAMCET Learning Team — Institutional Course Curation, Digitpen Hub LtdMy Skills:
- Curriculum Curation
- Course Content Review
- Learning Outcome Design
- Course Publishing & Quality Assurance
- Platform Content Operations
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Free
Course Includes
8 Chapters
16 Lectures
2 - 4 weeks
Skill Level intermediate
Taught in English
Lifetime Access
Certification of Completion
Category: University - Computer Engineering
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